In communication systems for digital transmission, a signal received by a receiver often contains a phase attributable, for example, to a phase variation created in frequency offset or signal rise in burst transmission. A phase lock loop circuit is provided on the receiver side in order to detect and correct the phase shift contained in the received signal.
Further, for communication systems for digital transmission, the received signal is influenced by distortion created in the transmission path. Therefore, in order to restore the received signal which has been deteriorated by the transmission path distortion, an equalizer or a signal estimator is provided on the receiver side.
To this end, a phase lock loop circuit using a signal estimator is provided on the receiver side in communication systems for digital transmission to remove the transmission path distortion and, at the same time, to correct the phase shift.
The construction of a conventional phase lock loop circuit using a signal estimator described in Japanese Patent Application No. 135454/1997 will be described with reference to FIG. 1 (block diagram).
This conventional phase lock loop circuit using a signal estimator comprises a phase rotator 102, a delay element 120, a signal estimator 303, a replica generator 112, a phase detector 113, a filter 114, and VCO (a voltage controlled oscillator) 115.
The phase rotator 102 rotates the phase of a received signal 117 input through an input terminal 101 based on a signal generated by VCO 115 to correct the phase shift contained in the received signal 117.
The signal estimator 303 estimates a transmission signal series from the distorted received signal by a Viterbi algorithm, and outputs an estimated signal 116.
The replica generator 112 performs a convolution operation of a previously determined transmission path impulse response value and the estimated signal 116 estimated by the signal estimator 303 to generate a replica signal 118 of the received signal 117 which is then output.
The phase detector 113 detects the phase difference between the replica signal 118 generated in the replica generator 112 and a signal output from the delay element 120. In this case, when the received signal 117 involves a frequency offset, the phase between the transmitted signal and the received signal changes with the elapse of time. This leads to a change in phase difference detected by the phase detector 113 with the elapse of time.
In the replica generator 112, the transmission path impulse response value used in the convolution operation is constant. Therefore, the replica signal 118 is output which does not suffer from phase variation so far as any error does not occur in the signal estimator 303. Since, however, the output signal of the delay element 120 suffers from a phase change, this phase difference is output from the phase detector 113.
The delay element 120 outputs the signal output from the phase rotator 102 by the quantity of delay equal to that created in the signal estimator 303. This permits the timing of the replica signal 118 output from the replica generator 112 to be synchronized with the timing of the signal output from the delay element 120.
The filter 114 filters the phase difference detected by the phase detector 113, and then outputs the bandwidth-limited VCO 115.
VCO 115 outputs a signal, of which the frequency is controlled by the signal output from the filter 114, to the phase rotator 102.
In this case, the phase detector 113, the filter 114, VCO 115, the phase rotator 102 operates as feedback loop means.
Next, the operation of this conventional phase lock loop circuit using an signal estimator will be explained.
The phase of the phase shift-containing received signal 117 input through the input terminal 101 is rotated by the phase rotator 102, and the signal is then input into the delay element 120 and the signal estimator 303. At the beginning of the operation of the phase lock loop circuit, a signal output from the phase rotator 102 contains a phase shift.
In the signal estimator 303, a transmission signal series is estimated from the phase-rotated received signal using Viterbi algorithm, and the signal estimator 303 outputs the estimate signal 116. The delay element 120 delays the signal output from the phase rotator 102 by the quantity of delay equal to that created in the signal estimator 303, and then outputs the delayed signal.
The phase detector 113 detects the phase difference between the replica signal 118 generated in the replica generator 112 and the signal output from the delay element 120. The phase difference detected by the phase detector 113 is bandwidth limited by the filter 114, and then input, as information on phase difference to be corrected, into VCO 115. The signal output from VCO 115 is input into the phase rotator 102, where the phase of the received signal 117 is rotated to correct the phase shift contained in the received signal 117.
In this conventional phase lock loop circuit using a signal estimator, control is performed toward a reduction in phase difference detected by the phase detector 113. Thus, the phase shift attributable, for example, to frequency offset contained in the received signal 117 is absorbed.
In this conventional phase lock loop circuit using a signal estimator, a phase error signal in the phase lock loop operation is generated from the series signal estimated in the signal estimator 303 using the replica signal 118. Therefore, phase lock correcting operation can be done with high accuracy even in the case of a received signal having large transmission path distortion.
In deciding the estimated signal in the conventional Viterbi algorithm, the so-called "traceback" is carried out wherein a decision is made in such a manner that the smallest path is selected among path metric values and traceback is then performed by a certain number from this path (for example, by 10 symbols) to determine the status of the path. The estimated signal 116 is output as a result of the decision.
In the conventional phase lock loop circuit using a signal estimator shown in FIG. 1, due to the constriction thereof, establishment of the estimated value by the series estimation in the signal estimator 303 causes some time delay. When the phase change rate is small, operation is performed without any problem even though the delay derived from the signal estimation in the signal estimator 303 is large. On the other hand, when the phase change rate has become large at the time of initial pulling or the like, the phase follow-up of the phase lock loop cannot catch up with the phase change, leading to divergence.
One method for increasing the phase follow-up speed of the phase lock loop is such that the frequency band of the filter 114 shown in FIG. 1 is broadened to increase the response speed of the phase lock loop. Broadening the frequency band of the filter 114, however, is likely to be influenced by disturbance such as noise. This deteriorates the follow-up accuracy of the phase shift.
Another method for increasing the phase follow-up speed of the phase lock loop is to decrease the estimation delay time of the signal estimator 303, thereby increasing the response speed. Decreasing the delay of the signal estimator 303, however, decreases the estimation ability of the signal estimator 303. Therefore, the estimated signal series contains many errors, making it impossible to correctly generate the replica signal 118. This in turn deteriorates the quality of information on the phase difference determined by the phase detector 113.
In this case, as with broadening of the frequency band of the filter 114, the follow-up of the phase lock loop is disturbed by the influence of noise or distortion contained in the received signal 117, making it impossible to correctly follow up the phase.
A further method for increasing the phase follow-up speed of the phase lock loop is described in Japanese Patent Application No. 238625/1998. In this method, a replica signal is generated using information on the minimum path metric in the signal estimator.
The construction of the conventional phase lock loop circuit using a signal estimator is shown in FIG. 2.
The conventional phase lock loop circuit shown in FIG. 2 is different from the conventional phase lock loop circuit shown in FIG. 1 in that the signal estimator 303 has been replaced with a signal estimator 103, the delay element 120 has been replaced with a delay element 106 and, instead of the estimated signal 116, a minimum path metric history signal 105 generated in the signal estimator 103 is input into the replica generator 112.
The construction of the signal estimator 103 is the same as that of the signal estimator 303, except that the function of outputting a minimum path metric history signal 105 has been newly added.
The minimum path metric history signal 105 is the result of the temporary estimation of the signal from the current path status without traceback in the decision of the estimated signal 116 in the conventional Viterbi algorithm. Since the minimum path metric history signal 105 is output without traceback, the delay time elapsed until the minimum path metric history signal 105 is output after the input of the signal into the signal estimator 103 is short.
For this reason, according to the conventional phase lock loop circuit shown in FIG. 2, the generation of the replica signal 118 using the minimum path metric history signal 105 can shorten the delay time of the whole phase lock loop circuit and can increase the response speed.
The delay time of the delay element 106 is a time corresponding to the time delay elapsed until, after the input of the received signal output from the phase rotator 102 into the signal estimator 103, the minimum path metric history signal 105 is generated in the signal estimator 103 followed by reproduction of the received signal using the minimum path metric history signal 105 in the replica generator 112.
According to the conventional phase lock loop circuit using a signal estimator which generates the replica signal 118 using the minimum path metric history signal 105, the delay time elapsed until the generation of the replica signal 118 can be shortened, contributing to increased response speed. Since, however, information in the course of estimation is used, the reliability of the replica signal 118 is lowered. In some transmission path status, due to error in the course of the estimation, the phase error cannot be accurately detected, resulting in divergence.
The conventional phase lock loop circuits using a signal estimator had the following problems.
(1) According to the generation of the replica signal using an estimated signal, the phase error can be detected accurately. Since, however, the response speed is so low that, when the phase change speed is high, the phase follow-up of the phase lock loop cannot catch up with the phase change, leading to divergence. PA1 (2) According to the generation of the replica signal using a minimum path metric history signal, the response speed can be increased. However, the reliability of the replica signal is so low that the phase error cannot be detected accurately.